MOnSter 6502 Bringup Status

MOnSter 6502 1 Comment

Wow, Maker Faire was totally nuts! Lots of people came by to check out the MOnSter 6502 and I had some interesting conversations with people. After taking a few days to recover, I dug back into the bringup and validation process.

The MOnSter 6502 now passes my basic validation test suite. I discovered two problems.

It was not booting consistently, and kept getting stuck in a bad state where the ‘1’ bit would run off the end of the instruction sequencer, or it would get stuck in a loop running the same (wrong) instruction over and over again. The RESG latch also was stuck on.

When RESET goes low, it turns on RESG. This forces the BRK instruction (which is meant to trigger a software interrupt) into the predecode IR (instruction register) by deasserting D1x1, sets the vector address to the reset vector (instead of the IRQ vector, as BRK normally does), and prevents BRK from writing to the stack so it can’t push the program counter and status bits. When BRK is done, it clears the RESG latch. This is a very clever hack that the original designers used so they could avoid having to run a reset line all over the chip.

Oddly, even when RESG was set (I could tell by a convenient LED), the contents of the IR were not all ‘0’ (again, according to convenient LEDs). Turns out the quad FET array devices used in the IR had some leads that were not soldered down correctly. Fixing that solved the problem.

After trying to run the validation suite again, it started failing the cycle-by-cycle validation on the first time an actual BRK instruction was supposed to be executed. BRK saves the least significant byte of the program counter the most significant byte, and finally the contents of the status register to the stack (with the B bit set so your interrupt service routine can tell the difference between BRK and a hardware IRQ). In this case, it was writing the most significant byte and the status register to the wrong locations in memory.

So I hard-wired the PHA (PusH Accumulator) instruction onto the data bus so I could observe a very simple instruction write to the stack. The value was written correctly, but instead of decrementing the stack pointer by 1, it subtracted 18! PHA decrements the SP by loading it onto the ADL bus and setting the ALU to add with the B input hold register connected to ADL and the A input hold register connected to the special bus. The idea is that by adding $FF you decrease the value by one. This only works if nothing else is driving the special bus except for the precharge pullup MOSFETs. It’s another clever hack from the original 6502 designers. In my case, instead of seeing $FF, the ALU was latching $EE! I tried adding a small amount of capacitance from special bus lines 0 and 4 to ground to keep the voltage up from the precharge cycle, and PHA then worked correctly. I ended up adding capacitors to all the bus lines just in case.

After those fixes my basic validation test suite passed without any further issues.

The next step is to run a more complete set of validation tests, and then BASIC!